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| H7N1004LD, H7N1004LS, H7N1004LM Silicon N-Channel MOSFET High-Speed Power Switching REJ03G0072-0600Z (Previous ADE-208-1552E(Z)) Rev.6.00 Aug.27.2003 Features * * * * Low on-resistance RDS(on) = 25 m typ. Low drive current Available for 4.5 V gate drive Outline LDPAK 4 D 4 4 G 1 S 1 2 3 1 2 2 H7N1004LS 3 3 H7N1004LM 1. Gate 2. Drain 3. Source 4. Drain H7N1004LD Rev.6.00, Aug.27.2003, page 1 of 11 H7N1004LD, H7N1004LS, H7N1004LM Absolute Maximum Ratings (Ta = 25C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body-drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID ID (pulse) IDR IAP Note 3 EAR Tch Tstg Note 3 Note 2 Note1 Value 100 20 30 100 30 15 22.5 50 150 -55 to +150 Unit V V A A A A mJ W C C Pch* Notes: 1. PW 10 s, duty cycle 1% 2. Value at Tc = 25C 3. Value at Tch = 25C, Rg 50 Rev.6.00, Aug.27.2003, page 2 of 11 H7N1004LD, H7N1004LS, H7N1004LM Electrical Characteristics (Ta = 25C) Item Symbol Min 100 V(BR)GSS 20 IGSS IDSS VGS(off) RDS(on) |yfs| Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDF trr -- -- 1.5 -- -- 22 -- -- -- -- -- -- -- -- -- -- -- -- Typ -- -- -- -- -- 25 30 37 2800 240 140 50 9 11 23 120 70 9.5 0.9 47 Max -- -- 10 10 2.5 35 45 -- -- -- -- -- -- -- -- -- -- -- -- -- Unit V V A A V m m S pF pF pF nC nC nC ns ns ns ns V ns IF = 30 A, VGS = 0 IF = 30 A, VGS = 0 diF/dt = 100 A/s Test conditions ID = 10 mA, VGS = 0 IG = 100 A, VDS = 0 VGS = 16 V, VDS = 0 VDS = 100 V, VGS = 0 ID = 1 mA, VDS = 10 V Note 1 ID = 15 A, VGS = 10 V Note 1 ID = 15 A, VGS = 4.5 V Note 1 ID = 15 A, VGS = 10 V Note 1 VDS = 10 V VGS = 0 f = 1 MHz VDD = 50 V VGS = 10 V ID = 30 A VGS = 10 V, ID = 15 A RL = 2 Rg = 4.7 Drain to source breakdown voltage V(BR)DSS Gate to source breakdown voltage Gate to source leak current Zero gate voltage drain current Gate to source cutoff voltage Static drain to source on state resistance Forward transfer admittance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate to source charge Gate to drain charge Turn-on delay time Rise time Turn-off delay time Fall time Body-drain diode forward voltage Body-drain diode reverse recovery time Notes: 1. Pulse test Rev.6.00, Aug.27.2003, page 3 of 11 H7N1004LD, H7N1004LS, H7N1004LM Main Characteristics Power vs. Temperature Derating 80 Pch (W) Maximum Safe Operation Area 200 100 Drain Current I D (A) 60 30 10 3 1 0.3 Operation in Channel Dissipation 40 1 = DC 10 ms ms (T Op ( c = e 1s 25 ratio hot) C n ) PW 10 10 0 s s 20 0.1 limited by RDS(on) 0.02 0.1 Ta = 25C 3 30 0.3 1 10 100 Drain to Source Voltage VDS (V) this area is 0 50 100 150 Tc (C) 200 Case Temperature Typical Output Characteristics 50 10 V 40 Drain Current I D (A) Typical Transfer Characteristics 50 V DS = 10 V Pulse Test 40 Drain Current I D (A) Pulse Test 6V 4V 30 3.5 V 30 20 20 -25C 25C Tc = 75C 10 VGS = 3 V 0 2 4 6 8 10 Drain to Source Voltage V DS (V) 10 0 3 4 5 1 2 Gate to Source Voltage V GS (V) Rev.6.00, Aug.27.2003, page 4 of 11 H7N1004LD, H7N1004LS, H7N1004LM Drain to Source Saturation Voltage VS. Gate to Source Voltage 1.0 Drain to Source Saturation Voltage V DS(on) (V) Pulse Test Drain to Source on State Resistance RDS(on) (m) Static Drain to Source on State Resistance vs. Drain Current 500 Pulse Test 200 100 50 0.8 0.6 I D = 20 A 0.4 10 A 0.2 5A V GS = 4.5 V 10 V 20 10 5 0 5 10 15 20 1 2 Gate to Source Voltage VGS (V) 5 10 20 50 Drain Current I D (A) 100 Static Drain to Source on State Resistance RDS(on) (m) Forward Transfer Admittance |yfs| (S) Static Drain to Source on State Resistance vs. Temperature 100 Pulse Test 80 I D = 20 A 60 5, 10 A Forward Transfer Admittance vs. Drain Current 100 Tc = -25C 10 1 25C 40 V GS = 4.5 V 5, 10 A V GS = 10 V I D = 20 A 0.1 75C V DS = 10 V Pulse Test 20 0 -25 0 25 50 75 100 125 150 (C) 0.01 0.01 0.1 1 10 100 Case Temperature Tc Drain Current I D (A) Rev.6.00, Aug.27.2003, page 5 of 11 H7N1004LD, H7N1004LS, H7N1004LM Body-Drain Diode Reverse Recovery Time 100 10000 5000 Typical Capacitance vs. Drain to Source Voltage Reverse Recovery Time trr (ns) Capacitance C (pF) Ciss 2000 1000 500 200 100 50 50 Coss Crss VGS = 0 f = 1 MHz 0 10 20 30 40 50 Drain to Source Voltage V DS (V) 20 di / dt = 100 A / s V GS = 0, Ta = 25C 0.3 1 3 10 30 100 Reverse Drain Current I DR (A) 20 10 10 0.1 Dynamic Input Characteristics 200 Switching Characteristics 20 1000 Drain to source Voltage V DS (V) Switching Time t (ns) VDD = 25 V 50 V 160 100 V I D = 30 A 120 Gate to Source Voltage V GS (V) VGS 16 V GS = 10 V, V DD = 30 V PW = 5 s, duty 1% R G = 4.7 100 tr 12 t d(off) t d(on) 80 8 10 tf 40 VDD = 100 V 50 V 25 V 20 40 60 80 Gate Charge Qg (nC) 4 VDS 0 100 0 1 0.1 0.3 1 3 10 30 Drain Current I D (A) 100 Rev.6.00, Aug.27.2003, page 6 of 11 H7N1004LD, H7N1004LS, H7N1004LM Reverse Drain Current vs. Source to Drain Voltage 50 Reverse Drain Current I DO (A) Maximum Avalanche Energy vs. Channel Temperature Derating EAR (mJ) 40 I AP = 15 A V DD = 50 V duty < 0.1 % Rg > 50 0, -5 V 40 V GS = 10 V 32 Repetitive Avalanche Energy 30 5V 20 24 16 10 Pulse Test 0 0.4 0.8 1.2 1.6 VSD (V) 2.0 Source Drain Voltage 8 0 25 50 75 100 Channel Temperature 125 150 Tch (C) Avalanche Test Circuit EAR = Avalanche Waveform 1 2 * L * I AP * 2 VDSS VDSS - V DD V DS Monitor L I AP Monitor V (BR)DSS I AP VDD ID V DS Rg Vin 15 V D. U. T 50 0 VDD Rev.6.00, Aug.27.2003, page 7 of 11 H7N1004LD, H7N1004LS, H7N1004LM Normalized Transient Thermal Impedance vs. Pulse Width 3 Normalized Transient Thermal Impedance s (t) Tc = 25C 1 D=1 0.5 0.2 0.3 0.1 0.1 0.05 0.02 1 0.0 lse pu ot h 1s ch - c(t) = s (t) * ch - c ch - c = 2.5C/ W, Tc = 25C PDM PW T 0.03 D= PW T 0.01 10 100 1m 10 m 100 m 1 10 Pulse Width PW (s) Switching Time Test Circuit Vin Monitor Rg D.U.T. RL Vin Vin 10 V V DS = 30 V Vout Monitor Switching Time Waveform 90% 10% 10% 90% td(on) tr 90% td(off) tf 10% Vout Rev.6.00, Aug.27.2003, page 8 of 11 H7N1004LD, H7N1004LS, H7N1004LM Package Dimensions * H7N1004LD As of January, 2003 Unit: mm (1.4) 4.44 0.2 10.2 0.3 1.3 0.15 11.3 0.5 0.3 10.0 + 0.5 - 8.6 0.3 1.3 0.2 1.37 0.2 0.76 0.1 2.54 0.5 2.54 0.5 11.0 0.5 0.2 0.86 + 0.1 - 2.49 0.2 0.4 0.1 Package Code JEDEC JEITA Mass (reference value) LDPAK (L) -- -- 1.40 g Rev.6.00, Aug.27.2003, page 9 of 11 H7N1004LD, H7N1004LS, H7N1004LM * H7N1004LS As of January, 2003 Unit: mm 4.44 0.2 10.2 0.3 (1.4) 8.6 0.3 + 0.3 - 0.5 10.0 (1.5) (1.5) 2.49 0.2 0.2 0.1 + 0.1 - 7.8 7.0 2.2 1.37 0.2 0.3 3.0 + 0.5 - 1.3 0.2 2.54 0.5 0.2 0.86 + 0.1 - 0.4 0.1 2.54 0.5 Package Code JEDEC JEITA Mass (reference value) LDPAK (S)-(1) -- -- 1.30 g Rev.6.00, Aug.27.2003, page 10 of 11 1.7 1.3 0.15 7.8 6.6 H7N1004LD, H7N1004LS, H7N1004LM * H7N1004LM As of January, 2003 Unit: mm 4.44 0.2 10.2 0.3 (1.4) 8.6 0.3 + 0.3 - 0.5 2.49 0.2 (2.3) 0.2 0.1 + 0.1 - (1.5) 10.0 7.8 7.0 2.2 1.37 0.2 1.3 0.2 2.54 0.5 0.4 0.1 0.3 5.0 + 0.5 - 0.2 0.86 + 0.1 - 2.54 0.5 Package Code JEDEC JEITA Mass (reference value) LDPAK (S)-(2) -- -- 1.35 g Rev.6.00, Aug.27.2003, page 11 of 11 1.7 1.3 0.15 7.8 6.6 Sales Strategic Planning Div. Keep safety first in your circuit designs! Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. 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Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon 0.0 |
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